Advanced VLSI Design & Verification
Superior Training Methodology
100% Placement Support
Industry Standard Tools
4.7/5 Rating
Expert Trainers
Available Courses in VLSI
Advanced VLSI Design
PG Diploma in VLSI
Advanced FPGA Design
Advanced VLSI Verification
ABOUT THE COURSE
The VLSI Design and Verification Team, conducts research and training in the areas of VLSI Design and Verification.
The courses start with an exploratory project and ends with a comprehensive project. We offer courses VLSI Design, VLSI Verification and FPGA System Design. The Design course includes an in-depth focus on Digital Design, Synthesis, Verilog, while Verification course includes writing testbenches using System Verilog and UVM methodologies. FPGA system design teaches Synthesis, Simulation and Implementation of VLSI Design targeting FPGAs.These courses are offered online and in-class mode. The Diploma in VLSI Design program includes VLSI Design, VLSI Verification and FPGA Implementation, together. This program is best suited for engineers starting their career in VLSI.
QUALIFICATIONS
Aggregate 50% marks or above in a Graduate degree (BE/B.Tech. or M.Sc) in Electronics Engineering & Telecommunication/ Electrical engineering/ Computer Science & Engineering/Instrumentation or Master of Computer Applications (MCA). (Students of 4th year engineering are also eligibile). For VLSI design course it’s essential to have good knowledge in Electronics where as for Embedded course its essential to have knowledge in C.
SELECTION
The course consists theory and practical classes spread over a period of about 15 weeks. The course will have about 100 contact hours and also hands-on practical lab sessions. Design project will be done in the time allotted for lab sessions. In addition, there will be guest lectures by experts from industry and academic institutions. Each course batch is limited to first 15 participants. Participants have to appear for a test of duration 30 min in Digital Design and general aptitude, Followed by Interview. The batch size is kept to minimum, this enables us to focus more on each student so, that we help them understand the concepts in depth.
INTERNSHIP
VLSI internships are designed for final year electronics / electrical engineering students of B.Tech/M.Tech/Phd (INDIA) and M.S/Phd (USA) and it starts with learning of concepts on VLSI Design, System On Chip Design, ASIC and FPGA design Flow, Digital Electronics & Verilog HDL which will be highly required to start an industry standard project. Doing this internship will make you a hands-on RTL Designer or hands-on Verification or Validation Engineer.
RESEARCH
VLSI research projects are designed for final year electronics / electrical engineering students of B.Tech/M.Tech/Phd (INDIA) and M.S/Phd (USA) and it starts with learning of concepts on VLSI Design, System On Chip Design, ASIC and FPGA design Flow, Digital Electronics & Verilog HDL which will be highly required to start an industry standard project. Doing these research projects will make you a hands-on RTL, Verification or Validation experience suitable for industry and MS/Phd studies.
KEY FEATURES
1. 24×7 Support on exercises.
2. Case studies
3. 4.7/5 rating
4. Industry standard tools
5. Two decade of experience
6. World class course structure
7. Expert mentorship on VLSI career
8. 100% Placement Support
9. Lifelong membership
1. Scholarship will be provided based on online test and technical interview performance.
2. Candidates with score 80% in Engineering and 90% above in online test will be selected.
3. Candidates with good GATE score can avail additional scholarship.T&C Apply
INFRASTRUCTURE
1. ARM Cortex Board
2. Arduino Board
3. Raspberry Pi Mod-4 IoT Board
4. Arduino Uno Board
5. ARM Cortex starter kit
6. Xilinx SPartan-6 starter kit
7. Xilinx Zync starter Kit
8. 100+ Variety of Sensors, PIC and Rabbit 5000 Microcontrollers
COURSE CURRICULLUM
Advanced VLSI Design
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps – Demo
- Components of UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits – Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits – Design and Analysis
- Memories and PLD
- Finite State Machine
Microcontroller Design
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Non Ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS circuit design
- Transistor sizing
- Layout and Stick Diagrams
- CMOS Processing Steps
- Fabrication
- CMOS Technology – Current Trends
[1] Introduction to Verlog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
[2] Data Types
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
[3] Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
[4] Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
[5] Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
[6] Advanced Verilog for Verification
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
[7] Synthesis Coding Style
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM – State, Arc and Sequence coverage
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loop
Advanced VLSI Verification
| Lecture 1 | Introduction to Verification Methodology | |
| Lecture 2 | Verification Process | |
| Lecture 3 | Reusable TB | |
| Lecture 4 | Verification Environment Architecture | |
| Lecture 5 | Constraint Random Coverage Driven Verification | |
| Lecture 6 | Verification Methodologies & Summary | |
| Quiz 1 | Knowledge Check |
| Lecture 7 | SV Concepts Agenda | |
| Lecture 8 | SV Overview | |
| Lecture 9 | SV Transactions | |
| Lecture 10 | SV Interface | |
| Lecture 11 | SV Virtual Interface | |
| Lecture 12 | SV OOP | |
| Lecture 13 | SV Randomization & Functional Coverage | |
| Lecture 14 | SV TB Architecture | |
| Quiz 2 | Knowledge Check – SV Concepts |
| Lecture 15 | SystemVerilog Introduction & Logic Data Type | |
| Lecture 16 | SV Data Types – 2 State, Struct & Enum | |
| Lecture 17 | SV Data Types – Strings,Packages & Summary | |
| Quiz 3 | Knowledge Check – Data Types |
| Lecture 18 | SV Memories – Introduction, Packed and Multi Dimensional Arrays | |
| Lecture 19 | SV Memories – Dynamic Arrays & Queues | |
| Lecture 20 | SV Memories – Associative Arrays, Array Methods & Summary | |
| Quiz 4 | Knowledge Check – Memories |
| Lecture 7 | SV Concepts Agenda | |
| Lecture 8 | SV Overview | |
| Lecture 9 | SV Transactions | |
| Lecture 10 | SV Interface | |
| Lecture 11 | SV Virtual Interface | |
| Lecture 12 | SV OOP | |
| Lecture 13 | SV Randomization & Functional Coverage | |
| Lecture 14 | SV TB Architecture | |
| Quiz 2 | Knowledge Check – SV Concepts |
| Lecture 23 | SV Interfaces – Introduction & Verilog ports Vs SV Interface | |
| Lecture 24 | SV Interfaces – Modports & Clocking Block | |
| Lecture 25 | SV Interfaces – Examples & Summary | |
| Quiz 6 | Knowledge Check – Interfaces |
| Lecture 26 | SV OOP – Introduction, Class Data Type & Objects | |
| Lecture 27 | SV OOP – Constructor, Null Object, Object assignments and copy | |
| Lecture 28 | SV OOP – Shallow Vs Deep Copy & Summary | |
| Quiz 7 | Knowledge Check – OOP Basics |
| Lecture 29 | SV OOP – Introduction, Inheritance & Super | |
| Lecture 30 | SV OOP – Static properties & methods and Pass by ref | |
| Lecture 31 | SV OOP – Polymorphism, $cast, Virtual & Parametrised classes, Summary | |
| Quiz 8 | Knowledge Check – OOP Advanced |
- Introduction to UVM, Getting started with UVM
- Monitors and Reporting
- Transaction-Level Modeling
- Checkers and Scoreboards
- Functional Coverage
- Random Stimulus Generation
- Factory and Configuration
- Agent Architecture
- Objections, Sequences, Layered Sequences and Agents
- Advanced Sequencer Topics
- UVM Register Layer
- AMBA APB/AHB/AXI Verification using SV and UVM
PG DIPLOMA in VLSI Design
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps – Demo
- Components of UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits – Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits – Design and Analysis
- Memories and PLD
- Finite State Machine
Microcontroller Design
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Non Ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS circuit design
- Transistor sizing
- Layout and Stick Diagrams
- CMOS Processing Steps
- Fabrication
- CMOS Technology – Current Trends
[1] Introduction to Verlog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
[2] Data Types
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
[3] Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
[4] Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
[5] Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
[6] Advanced Verilog for Verification
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
[7] Synthesis Coding Style
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM – State, Arc and Sequence coverage
FPGA Architecture
[1] PLD
- General Structure and Classification
- CPLD Vs FPGA
[2] Xilinx CPLD – Xc9500
- Block Diagram of CPLD
- Detailed study of each block
- Endurance limits
- Timing Model
[3] Xilinx FPGA
- FPGA Architecture
- CLBs and Input/Output Blocks
- Luts, SLICE DFFs
- Dedicated MUXes
- Programmable Interconnects
- Architectural Resources
- Power Distribution and Configuration
[4] FPGA Architecture of Different Xilinx Families
[5] Netlist and Timing simulation
- Project Specification Analysis
- Understanding the architecture
- Module level implementation and verification
- Building the top-level module
- Implementing the design into the FPGA board
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loop
- Directed Vs Random
- Functional verification process
- Stimulus Generation
- Bus function model
- Monitors and reference models
- Coverage Driven Verification
- Verification Planning and management
[1] Introduction to System Verilog
- New Data types
- Tasks and Functions
- Interfaces
- Clocking blocks
[2] Object Oriented Programming and Randomization
- OOP Basics
- Classes – Objects and handles
- Polymorphism and Inheritance
- Randomization
- Constraints
[3] Threads and Virtual Interfaces
- Fork Join
- Fork Join_any
- Fork Join_none
- Event controls
- Mailboxes and semaphores
- Virtual Interfaces
- Transactors
- Building verification environment
- Testcases
[4] Callbacks
- Facade Class
- Building Reusable Transactors
- Inserting Callbacks
- Registering Callbacks
[5] Direct Programming Interface
[6] Functional Coverage
- Coverage models
- Coverpoints and bins
- Cross coverage
- Regression testing
- Verification Plan
- TB Architecture
- Coverage Model
- Tracking the simulation process
- Building regression testsuite
- Testsuite optimization
- Environment Configuration
- Reference Models and Predictor Logics
- Using Legacy BFMs
- Scenario Generation
- Testcases – Random,
Directed and corner case
- Coding styles for VIP
- Introduction to ABV
- Immediate Assertions
- Simple Assertions
- Sequences
- Sequence Composition
- Advanced SVA Features
- Assertion Coverage
Verification and RTL sign-off
- Project specification analysis
- Defining verification plan
- Creating Testbench architecture
- Defining Transaction
- Implementing the transactors – Generator, Driver, Receiver and Scoreboard
- Implementing the coverage model
- Building the top level verification environment
- Defining weighted random, corner case and directed testcases
- Building the regression testsuite
- Generating the functional and code coverage reports
- Introduction to UVM Methodology
- Overview of Project
- UVM TB Architecture
- Stimulus Modeling
- Creating UVCs and Environment
- UVM Simulation Phases
- Testcase Classes
- TLM Overview
- Configuring TB Environment
- UVM Sequences
- UVM Sequencers
- Connecting DUT- Virtual Interface
- Virtual Sequences and Sequencers
- Creating TB Infrastructure
- Connecting multiple UVCs
- Building a Scoreboard
- Introduction to Register Modeling
- Building reusable environments
- Guest Lectures by Industry Experts
- Design specification analysis
- Creating the design architecture
- Partitioning the design
- RTL coding in Verilog
- RTL functional verification
- RTL Synthesis
- Place & Route the netlist
- Timing Simulation
- Transition from College to Corporate
- Interpersonal skills and Presentation Skills
- Email Etiquette
- Resume writing
- Interview Skills: Group Discussion and HR Round Preparation
- Mockup Interviews Technical/HR
FPGA Design
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps – Demo
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits – Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits – Design and Analysis
- Memories and PLD
- Finite State Machine
Microcontroller Design
[1] Introduction to Verlog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
[2] Data Types
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
[3] Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
[4] Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
[5] Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
[6] Advanced Verilog for Verification
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
[7] Synthesis Coding Style
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM – State, Arc and Sequence coverage
[1] PLD
- General Structure and Classification
- CPLD Vs FPGA
[2] Xilinx CPLD – Xc9500
- Block Diagram of CPLD
- Detailed study of each block
- Endurance limits
- Timing Model
[3] Xilinx FPGA
- FPGA Architecture
- CLBs and Input/Output Blocks
- Luts, SLICE DFFs
- Dedicated MUXes
- Programmable Interconnects
- Architectural Resources
- Power Distribution and Configuration
[4] FPGA Architecture of Different Xilinx Families
[5] Netlist and Timing simulation
- FPGA Design Flow – Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
- Optimal FPGA Design – HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
- Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains
- Implementation options including Map, PAR
- Bit File generation
- Develop Verilog Code
- Synthesis
- Implementation on Spartan-6
Frequently Asked Questions
Most frequent questions and answers
Can I get a job into VLSI Industry, as I am fresh college graduate?
Yes, industry is hiring trained fresh college graduates for entry level jobs. Many of our students have got placed in top product and services companies. Along, startups are relying on new college grads for fresh ideas and out of box thinking.
Do you have a free demo session, to get a feel of the trainer and understand my choice of field better, before payment?
Yes. You are always welcome! Send us a query or call us. We will arrange a 1 to 1 meeting with the trainer and counselor. They explain you course content, job opportunities and prerequisites.
Can I get an internship, after the coursework? What do I need to ensure?
We are connected with companies focused on IT, Analytics, IoT, VLSI and Embedded. After every training session, we send our candidate profiles to these companies based on their interest. Companies interview and select the candidates of their choice. However, we try our level best to get you an entry into your dream job.
I am not from electronics, neither do I have a engineering degree. Can I join?
At industry, degree is no constrain, but Skill is. At design nation, qualification is not prerequisite, but passion is. If you are passionate to shine in the area of interest, come and talk to us. We are here to help you!
Do you provide a certificate after completion of the course?
Yes. We provide a certificate after the course completion. You can add it to LinkedIn profile, resume and mention during the interviews. Companies prefer trained resources than untrained candidates.
Can I avail the scholarship at Design Nation?
Yes, our scholarships are for people like you, with great talent and financial needs. We are more than happy to help you, with the process. Please check the cutoffs for scholarships in above section. We helped many, and still counting!!
