FPGA Design
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps – Demo
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits – Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits – Design and Analysis
- Memories and PLD
- Finite State Machine
Microcontroller Design
[1] Introduction to Verlog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
[2] Data Types
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
[3] Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
[4] Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
[5] Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
[6] Advanced Verilog for Verification
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
[7] Synthesis Coding Style
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM – State, Arc and Sequence coverage
[1] PLD
- General Structure and Classification
- CPLD Vs FPGA
[2] Xilinx CPLD – Xc9500
- Block Diagram of CPLD
- Detailed study of each block
- Endurance limits
- Timing Model
[3] Xilinx FPGA
- FPGA Architecture
- CLBs and Input/Output Blocks
- Luts, SLICE DFFs
- Dedicated MUXes
- Programmable Interconnects
- Architectural Resources
- Power Distribution and Configuration
[4] FPGA Architecture of Different Xilinx Families
[5] Netlist and Timing simulation
- FPGA Design Flow – Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
- Optimal FPGA Design – HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
- Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains
- Implementation options including Map, PAR
- Bit File generation
- Develop Verilog Code
- Synthesis
- Implementation on Spartan-6