PG DIPLOMA in VLSI Design

• VLSI Design Flow
• ASIC Vs FPGA
• RTL Design Methodologies
• Introduction to ASIC Verification Methodologies

VLSI Design Flow Steps – Demo

• Components of UNIX system
• Directory Structure
• Utilities and Commands
• Vi Editor

• Introduction to Digital Electronics
• Arithmetic Circuits
• Data processing Circuits
• Universal Logic Elements
• Combinational Circuits – Design and Analysis
• Latches and Flip flops
• Shift Registers and Counters
• Sequential Circuits – Design and Analysis
• Memories and PLD
• Finite State Machine

Microcontroller Design

• Introduction to STA
• Comparison with DTA
• Timing Path and Constraints
• Different types of clocks
• Clock domain and Variations
• Clock Distribution Networks
• How to fix timing failure

• Non Ideal characteristics
• BJT vs FET
• CMOS Characteristics
• CMOS circuit design
• Transistor sizing
• Layout and Stick Diagrams
• CMOS Processing Steps
• Fabrication
• CMOS Technology – Current Trends

[1] Introduction to Verlog HDL

• Applications of Verilog HDL
• Verilog HDL language concept
• Verilog language basics and constructs
• Abstraction levels

[2] Data Types

• Type Concept
• Nets and registers
• Non hardware equivalent variables
• Arrays

[3] Verilog Operators

• Logical operators
• Bitwise and Reduction operators
• Concatenation and conditional
• Relational and arithmetic
• Shift and Equality operators
• Operators precedence

[4] Assignments

• Type of assignments
• Continuous assignments
• Timing references
• Procedures
• Blocking and Non-Blocking assignments
• Execution branching
• Tasks and Functions

[5] Finite State Machine

• Basic FSM structure
• Moore Vs Mealy
• Common FSM coding styles
• Registered outputs

[6] Advanced Verilog for Verification

• System Tasks
• Internal variable monitoring
• Compiler directives
• File input and output

[7] Synthesis Coding Style

• Registers in Verilog
• Unwanted latches
• Operator synthesis
• RTL Coding style

• Statement coverage
• Branch Coverage
• Expression Coverage
• Path Coverage
• Toggle Coverage
• FSM – State, Arc and Sequence coverage

FPGA Architecture

[1] PLD

• General Structure and Classification
• CPLD Vs FPGA

[2] Xilinx CPLD – Xc9500

• Block Diagram of CPLD
• Detailed study of each block
• Endurance limits
• Timing Model

[3] Xilinx FPGA

• FPGA Architecture
• CLBs and Input/Output Blocks
• Luts, SLICE DFFs
• Dedicated MUXes
• Programmable Interconnects
• Architectural Resources
• Power Distribution and Configuration

[4] FPGA Architecture of Different Xilinx Families

[5] Netlist and Timing simulation

• Project Specification Analysis
• Understanding the architecture
• Module level implementation and verification
• Building the top-level module
• Implementing the design into the FPGA board

• Introduction to Perl
• Functions and Statements
• Numbers, Strings, and Quotes
• Comments and Loop