COURSE CURRICULLUM
Advanced VLSI Design
- VLSI Design Flow
- ASIC Vs FPGA
- RTL Design Methodologies
- Introduction to ASIC Verification Methodologies
VLSI Design Flow Steps – Demo
- Components of UNIX system
- Directory Structure
- Utilities and Commands
- Vi Editor
- Introduction to Digital Electronics
- Arithmetic Circuits
- Data processing Circuits
- Universal Logic Elements
- Combinational Circuits – Design and Analysis
- Latches and Flip flops
- Shift Registers and Counters
- Sequential Circuits – Design and Analysis
- Memories and PLD
- Finite State Machine
Microcontroller Design
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Non Ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS circuit design
- Transistor sizing
- Layout and Stick Diagrams
- CMOS Processing Steps
- Fabrication
- CMOS Technology – Current Trends
[1] Introduction to Verlog HDL
- Applications of Verilog HDL
- Verilog HDL language concept
- Verilog language basics and constructs
- Abstraction levels
[2] Data Types
- Type Concept
- Nets and registers
- Non hardware equivalent variables
- Arrays
[3] Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and conditional
- Relational and arithmetic
- Shift and Equality operators
- Operators precedence
[4] Assignments
- Type of assignments
- Continuous assignments
- Timing references
- Procedures
- Blocking and Non-Blocking assignments
- Execution branching
- Tasks and Functions
[5] Finite State Machine
- Basic FSM structure
- Moore Vs Mealy
- Common FSM coding styles
- Registered outputs
[6] Advanced Verilog for Verification
- System Tasks
- Internal variable monitoring
- Compiler directives
- File input and output
[7] Synthesis Coding Style
- Registers in Verilog
- Unwanted latches
- Operator synthesis
- RTL Coding style
- Statement coverage
- Branch Coverage
- Expression Coverage
- Path Coverage
- Toggle Coverage
- FSM – State, Arc and Sequence coverage
- Introduction to Perl
- Functions and Statements
- Numbers, Strings, and Quotes
- Comments and Loop
Advanced VLSI Verification
| Lecture 1 | Introduction to Verification Methodology | |
| Lecture 2 | Verification Process | |
| Lecture 3 | Reusable TB | |
| Lecture 4 | Verification Environment Architecture | |
| Lecture 5 | Constraint Random Coverage Driven Verification | |
| Lecture 6 | Verification Methodologies & Summary | |
| Quiz 1 | Knowledge Check |
| Lecture 7 | SV Concepts Agenda | |
| Lecture 8 | SV Overview | |
| Lecture 9 | SV Transactions | |
| Lecture 10 | SV Interface | |
| Lecture 11 | SV Virtual Interface | |
| Lecture 12 | SV OOP | |
| Lecture 13 | SV Randomization & Functional Coverage | |
| Lecture 14 | SV TB Architecture | |
| Quiz 2 | Knowledge Check – SV Concepts |
| Lecture 15 | SystemVerilog Introduction & Logic Data Type | |
| Lecture 16 | SV Data Types – 2 State, Struct & Enum | |
| Lecture 17 | SV Data Types – Strings,Packages & Summary | |
| Quiz 3 | Knowledge Check – Data Types |
| Lecture 18 | SV Memories – Introduction, Packed and Multi Dimensional Arrays | |
| Lecture 19 | SV Memories – Dynamic Arrays & Queues | |
| Lecture 20 | SV Memories – Associative Arrays, Array Methods & Summary | |
| Quiz 4 | Knowledge Check – Memories |
| Lecture 7 | SV Concepts Agenda | |
| Lecture 8 | SV Overview | |
| Lecture 9 | SV Transactions | |
| Lecture 10 | SV Interface | |
| Lecture 11 | SV Virtual Interface | |
| Lecture 12 | SV OOP | |
| Lecture 13 | SV Randomization & Functional Coverage | |
| Lecture 14 | SV TB Architecture | |
| Quiz 2 | Knowledge Check – SV Concepts |
| Lecture 23 | SV Interfaces – Introduction & Verilog ports Vs SV Interface | |
| Lecture 24 | SV Interfaces – Modports & Clocking Block | |
| Lecture 25 | SV Interfaces – Examples & Summary | |
| Quiz 6 | Knowledge Check – Interfaces |
| Lecture 26 | SV OOP – Introduction, Class Data Type & Objects | |
| Lecture 27 | SV OOP – Constructor, Null Object, Object assignments and copy | |
| Lecture 28 | SV OOP – Shallow Vs Deep Copy & Summary | |
| Quiz 7 | Knowledge Check – OOP Basics |
| Lecture 29 | SV OOP – Introduction, Inheritance & Super | |
| Lecture 30 | SV OOP – Static properties & methods and Pass by ref | |
| Lecture 31 | SV OOP – Polymorphism, $cast, Virtual & Parametrised classes, Summary | |
| Quiz 8 | Knowledge Check – OOP Advanced |
- Introduction to UVM, Getting started with UVM
- Monitors and Reporting
- Transaction-Level Modeling
- Checkers and Scoreboards
- Functional Coverage
- Random Stimulus Generation
- Factory and Configuration
- Agent Architecture
- Objections, Sequences, Layered Sequences and Agents
- Advanced Sequencer Topics
- UVM Register Layer
- AMBA APB/AHB/AXI Verification using SV and UVM
